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Portmaster Adapter/A
Multiport Adapter Model II
Electrical Interface Board Information
for
Hardware Developers
Second Edition (August 1996)
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The information contained in this document has not been submitted to any formal IBM test and is distributed on an "AS IS" basis without any warranty either expressed or implied. The use of this document or the implementation of any of these techniques is a customer responsibility and depends on the customer's ability to evaluate and integrate them into the customer's operational environment. While each item may have been reviewed by IBM for accuracy in a specific situation, there is no guarantee that the same or similar results will be obtained elsewhere. Customers attempting to adapt these techniques to their own environments do so at their own risk.
This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. IBM may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time.
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© Copyright International Business Machines Corporation 1991. All rights reserved.
Chapter 2. Interface Board Architecture
Chapter 3. Functional Interface
Chapter 4. Power Availability and Electrical Considerations
Chapter 5. Thermal Considerations
Chapter 6. Mechanical Hardware
Chapter 7. Diagnostic Support Strategy
References in this publication to IBM products, programs, or services do not imply that IBM intends to make these available in all countries in which IBM operates.
Any reference to an IBM licensed program or other IBM product in this publication is not intended to state or imply that only IBM's program or other product may be used.
The following terms, DENOTED BY AN ASTERISK (*), used in this publication, are trademarks or service marks of IBM Corporation in the United States and/or other countries:
IBM Personal System/2 Portmaster OS/2 Operating System/2 Micro Channel
The following terms, DENOTED BY A DOUBLE ASTERISK (**), used in this publication, are trademarks of other companies as follows:
Intel Intel Corporation Signetics Signetics Corporation Zilog Zilog Corporation
This publication contains hardware development information and techniques that may be applied to the design of an Interface Board that attaches to either the IBM* Realtime Co-Processor Portmaster* Adapter/A or the IBM Realtime Co-Processor Multiport Adapter, Model II.
Note: Throughout this publication, the general term co-processor adapter is used to designate either feature card named above. Unless otherwise stated, the information contained herein applies to both co-processor adapter cards.
The objectives of this publication are to provide the following for the Interface Board:
The information in this publication is intended for hardware designers, engineers, and individuals with a knowledge of electronics and/or programming who wish to design an Interface Board that attaches to the co-processor adapter.
It is assumed that the reader is familiar with the co-processor adapter, the applications in use, and programming. Therefore, terminology is not explained herein, except for terms that may be specially implemented.
The information contained in this publication is organized as follows:
This publication contains instructions for installing and setting up the Realtime Interface Co-Processor Portmaster Adapter/A, as well as the optional Interface Boards and cables.
This publication contains instructions for installing and setting up the Realtime Interface Co-Processor Multiport Adapter, Model II, as well as the optional Interface Boards and cables.
This library is used to isolate and repair a faulty field-replaceable unit. It provides instructions for problem isolation to help identify a faulty unit. Removal and replacement procedures are presented to complete the repair.
This publication describes the programmer interfaces to the Realtime Control Microcode.
This publication provides information necessary to interface the co-processor adapter through the system unit DOS. It describes all functions and capabilities, as well as installation, of the Realtime Control Microcode DOS Support software.
This publication is a productivity aid that provides the system developer with a variety of services to ease the writing of systems applications for the Realtime Interface Co-Processor family of adapters. It includes numerous task, event, resource, and communications services that allow the system developer to concentrate on the application instead of the system.
This publication provides information necessary to interface the co-processor adapter through the system unit Operating System/2* (OS/2*). It describes all functions and capabilities, as well as installation, of the Realtime Control Microcode OS/2 Support software.
This publication is a productivity aid which allows programmers to develop code for the co-processor adapter in the C programming language. It explains the C interface routines and the method of compiling and linking C tasks for the co-processor adapter.
One or more of the following publications might be needed for reference when using this publication.
Interface Boards can be built to attach to either the IBM Realtime Interface Co-Processor Portmaster Adapter/A or to the IBM Realtime Interface Co-Processor Multiport Adapter, Model II. The Portmaster Adapter/A allows Micro Channel* connectivity and Bus Master capability; whereas, the Multiport Adapter, Model II allows connectivity to the PC/AT bus. The mechanical design of both co-processor adapter cards is such that one Interface Board (IB) can install on either co-processor adapter card. The mounting differences are few; only a bracket and minor hardware mounting changes are required. The distance between the Interface Board and the co-processor adapter card varies, depending upon which co-processor adapter card is used. Refer to Chapter 6. "Mechanical Hardware" for specific values.
With the exception of processor speeds, system clocks, and overall DMA performance, the interface is the same for both co-processor adapter cards. The Portmaster Adapter/A operates at a clock frequency of 12.5 MHz, and the Multiport Adapter, Model II operates at a clock frequency of 10 MHz.
A co-processor adapter card has an 80C186 microprocessor for central processing of data on the card. A partial 80C186 system bus is provided at the IB interface. See Figure 1. This partial system bus includes 16 bits of address, 8 bits of data, and various control lines.
A co-processor adapter card can support various sizes of dynamic random access memory (DRAM). Up to 2M bytes of DRAM are supported on the Portmaster Adapter/A card, and 1M byte is supported on the Multiport Adapter, Model II card. This DRAM area can be accessed by the 80C186; it also can be accessed through the IB interface using the DMA Peripheral Interface Chip (DMAPIC). For the Portmaster Adapter/A card, the DRAM can be accessed from the Micro Channel via the RAM Controller and Bus Master Interface Chip (RCBMIC). For the Multiport Adapter, Model II card, the DRAM can be accessed from the PC bus using the Shared Storage Interface Chip (SSIC).
The DMAPIC has 16 independent DMA channels that are fully programmable. Eight of these DMA channels are hard-wire dedicated to the two Signetics Dual Serial Controller Chips (DUSCCs), SCC0 and SCC1, located on the co-processor adapter card. These two DUSCCs provide four serial ports of data and modem control signals. The data and modem control signals are available at the IB interface, and can be conditioned with drivers and receivers to provide connectivity to various electrical communication interfaces. See Figure 2. The remaining eight DMA channels are available to service various IB devices, such as two additional DUSCCs.
The DMAPIC has six sets of interrupt/interrupt acknowledge lines, four of which are used on the co-processor adapter card; the remaining two lines are available at the IB interface.
Chip select lines have been provided specifically for additional DUSCCs. These lines are available at the IB interface, and may possibly be used to select devices other than DUSCCs on an IB, if carefully used.
Two Zilog Counter/Timer Parallel I/O Units (CIO chips, CIO0 and CIO1) reside on the co-processor adapter card. The CIOs each have two parallel 8-bit I/O ports that are wired directly to the IB interface. The bits of these ports are bidirectional and individually programmable. In addition to the four 8-bit ports, CIO1 provides a 4-bit port which is accessible at the IB interface. The CIOs also have various timers that can be accessed via the ports.
Various other chip select lines are provided for I/O space that has been allocated for use on an IB.
A general-purpose register (Enables Register) is provided on the co-processor adapter card. The outputs of this register are wired to the IB interface and function as general-purpose control lines.
All Interface Boards must be assigned a single-byte ID by the Boca Raton MSP Co-Processor Hardware Development Group. Contact your IBM Marketing Representative to obtain an Interface Board ID assignment. It is recommended that all IBs implement IB ROS as described in this document, and that the ID be written to an architected address within this ROS. In certain instances, where an IB ROS is not implemented, the hardware must provide the facility to read the ID from I/O address 86h.
If the ID is implemented in IB ROS, it will be located in the Header section, and can be accessed by an I/O read to address E000h. This implementation also requires that a read to I/O address 86h result in a value of FFh. A chip select that decodes 86h has been provided; see "Timing Diagram for ROS and RDID86 Chip Select Signals".
The IB ROS provides 4KB of address space, which is accessible in I/O space from E000h to EFFFh. Structures, which are used to provide information about the communication ports, have been architected in the IB ROS. The data contained in these structures is then incorporated into the Port Configuration Descriptor (PCD), for use by the Realtime Control Microcode and Extended Services. The ROS also contains a mechanism for executable routines; see "Read Cable_ID Executable Routine".
A detailed discussion of PROM implementation is provided see section Prom Implementation and Other Uses.
Figure 1. Block Diagram of Co-Processor Adapter
+--------+ +-+ +----------+ +-----+
| | | | |Gate Array+-------Address------------>| D |
| |<---Data----------->| |<----->| | | R |
| Micro | |D| | RAM |<------Data--------------->| A |
|Channel | |r| |Controller| | M |
| or | |i| | & |-------RAM Control-------->| |
| PC Bus |<---Address-------->|v|<----->|Bus Master| +-----+
| | |e| | Interface|
| | |r| | (RCBMIC) |
| | | | | |
| |<---Control-------->| |<----->| (Note 2) |
| | | | +--+---+---+
| | +-+ ^ ^
+--------+ | |
+-+ V | +---------+
|8|<-Control----+--------------------------+---|----------------------------------------->| |
|0| | | | |
|C| | V | |
|1|<-AD0-AD15,--|--+---------------------------+-----------------------------AD8-AD15 --->| |
|8| A16-A19 | | +-+ +----------------------BAD0-BAD7--->| |
|6| | | |D| | 1 | I |
| | | | |r| | 0+---+ Data & Modem | B |
|C+------+ | |<------>|i| BAD0-BAD7 | +-+-+ | Control | |
|P|<-+ H| | | |v|<----------------+-----+---+-------->| D | |<------------->| I |
|U| H| O| | | |e| ^ | +---->| U | | | n |
+-+ O| L| | | |r| | | | +->| S | | | t |
L| D| | | +-+ V | | | | C | | | e |
D| A| | |<---------------+ +-+--+ | | | | C +-+ | r |
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