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Complex Introduction
Dates
Complex FCC IDs Complex Announcement Dates Complex Related Announcement Letters Complex FCC IDs Type 0 386DX-20 T0- is ??? 386DX-20 w/64KB T0 is ANO38620C1A Type 1 SX20 G is ANOIBM ??? DX-33 K is ANOIBM486A33 DX-25 J is ANOIBM486A25 DX2-66 is ANOIBM486B33 DX-50 is ANOIBM486A50 NOTE: The "G" was never released by itself as an upgrade. Though... the T0 complexi could be upgraded to the "G". We have a T0- BIOS with a date of Sept 1989. Early J and K complexi had a second socket for a Weitek 4167. Later versions only had solder pads for a socket. The late production J and K complexi had the space for a socket covered with small SMD components and green resist. As surmised before, the T1-50 "Big 50" was released to allow 486DX-50 power without ECC support without the need for the double-deck M. I'm not so sure that is the case... 191-198 IBM PS/2 486SX/25, 486/33 And 486/50 Processor Upgrade Opts Oct 17, 1991 192-101 IBM PS/2 Enhanced 486/50 Processor Upgrade Option Apr 28, 1992 Here is my SWAG... Get your Dr Dentons with footies out of the oven, put 'em on, grab a piping hot mug of mint truffle cocoa, and pile onto the sofa.... IBM introduced the G, J, and K in Oct 90. Supposedly. The T1-50 was released in Jun 1991. This might have been due in some measure to the initially low yield rates for the Intel 486DX-50. So far, there is no SOD version of the T1-50, which suggests the T1-50 is similar to the non-SOD K. This is where we will never know. My guess is the T1-50 was perhaps memory or I/O bound as compared to the M. The M adds buffering on both address and data lines [IIRC]. But adding another buffer on a T1 complex would run into a problem of physical space. Peter points out the distance limits between the 486DX-50 cache controller chipset, the L2 cache, and the CPU. IBM juggled things around and loaded up the daughtercard... So, while trying to correct the first issue, IBM ran into a whole 'nother conundrum... Type 2 486SX-2/50 H is ANOIBM486SXB25 486DX-2/50 L is [same FCCID as H] NOTE: Both the H and L use the same FCCID. Type 3 486DX-50 M is ANOIBM486B50 NOTE: I think the T1-50 was somewhat memory or I/O impaired, and IBM added another buffer. "Although Base 1 allows both the processor and busmasters to access memory concurrently through two paths, the Base 3 and 4 has buffers at both paths to provide better performance. Also the buffer on the adapter side (I/O buffer) uses packet data transfers for writes. This means 16 bytes are collected and this packet is written in one cycle to memory as opposed to writing for every 4 bytes received (as with unbuffered systems). " Type 4 486DX2-66 N is ANOIBM486C66 P60 P is ANOIBM586A60??? P66 Q is ANOIBM586A66 P90 Y is ANOIBM586A90??? Complex Announcement Dates Base 0 / Type 0 "T0-" Maybe late 1989? "T0" Base 1 / Type 1 "G" 486SX 20 MHz (announced Oct 1990) "J" 486DX 25 MHz (announced Oct 1990) "K" 486DX 33 MHZ (announced Oct 1990) Upgrade 486DX 50 MHz (announced June 1991) Upgrade 486DX2 66/33 (announced Aug 1992) Base 2 / Type 2 "H" / Upgrade 486SX 25 MHz (ann Oct 1991) "L" / Upgrade 486DX2 50/25 (ann April 1992) Base 3 / Type 3 "M"/ Upgrade 486DX 50 MHz (ann April 1992) Base 4 / Type 4 "N" / Upgrade 486DX2 66/33 MHz (ann Sept 1993) "P" / Upgrade Pentium 60 MHz (ann Aug 1993) "Q" / Upgrade Pentium 66 MHz (ann Sept 1993) "Y" / Upgrade Pentium 90/60 MHz (ann Oct 1994) Complex Related Announcement Letters 190-175 IBM PS/2 Model 95 XP 486 (8595-0J9, -0JD And -0KD) Oct 30, 1990 190-176 IBM PS/2 Model 90 XP 486 (8590-0J5, -0J9 And -0KD) Oct 30, 1990 190-186 IBM PS/2 486/33 Processor Upgrade Option Oct 30, 1990 191-052 IBM PS/2 486/25 and 486/33 Processor Upgrade Options Apr 23, 1991 191-057 IBM PS/2 Model 90 XP 486 (8590-0G5 And 0G9) Apr 23, 1991 191-058 IBM PS/2 Model 95 XP 486 (8595-0JF And 0KF) Apr 23, 1991 191-059 IBM PS/2 Model 95 XP 486 (8595-0G9 And 0GF) Apr 23, 1991 191-096 IBM PS/2 486/50 Processor Upgrade Option dated June 11, 1991 191-103 IBM PS/2 486/50 Processor Upgrade Upgrade Availability Jun 25, 1991 191-194 IBM PS/2 Model 95 XP 486 (8595-0H9 And 0HF) Oct 17, 1991 191-195 IBM PS/2 Model 90 XP 486 (8590-0H5 And 0H9) Oct 17, 1991 191-196 IBM PS/2 Model 90 XP 486 (8590-0K9 And 0KF) Oct 17, 1991 191-198 IBM PS/2 486SX/25, 486/33 And 486/50 Processor Upgrade Opts Oct 17, 1991 192-096 IBM PS/2 Model 95 XP 486 (8595-0MF And 0MT) Apr 28, 1992 192-097 IBM PS/2 Model 95 XP 486 (8595-0LF) Apr 28, 1992 192-099 IBM PS/2 486DX2-50 Processor Upgrade Option Apr 28, 1992 192-100 IBM PS/2 486-25/50 Microprocessor Upgrade Option Apr 28, 1992 192-101 IBM PS/2 Enhanced 486/50 Processor Upgrade Option Apr 28, 1992 192-178 IBM PS/2 486DX2-66 Processor Upgrade Option Aug 11, 1992 192-225 IBM PS/2 Model 95 XP 486 (9595-0LF, 0MF And 0MT) Sep 21, 1992 193-292 PS/2 Server 95 Array 466, 560 And 566 October 5, 1993 193-293 PS/2 Server 95 466, PS/55 466 And PS/2 Processor Upgrade Options Oct 5, 1993 194-360 IBM PS/2 90MHz Processor Upgrade Option w/Pentium Technology Oct 17, 1994 391-167 IBM PS/2 486SX/25 Processor Upgrade Promotion Oct 17, 1991 |