Specifications 
    Memory supported, cache, features
    Support for >1GB Disks as IML Drive 
    False ARTIC Diag Error
Type 3 Evergreen cpu upgrade that worked
"M"/ Upgrade 486DX 50 MHz   57F1597
    Daughtercard
      Why DX50 is on a Daughtercard
       Downlevel Complex Incompatible with some Streamers  [Uplevel is 82G2484]
      Daughtercard Rework
         Rework on Right
         Rework on Left
    Base Board
    Diagnostic LEDs
  Enhanced Dual Path Memory Parts
U27 Burning 

DX50 Base Board

U27 BIOS. Mitsubishi variant of the 27C201, (256K x 8-bit.)
87X0079 What is this? It's on all later complexes.

J2 Header between Base and Daughter cards. 10x11 on left, 10x13 on right, 240 pins total.

OS2 22.1184 MHz Osc -
          Clock for "Type 3 High-Speed UART" - all DMA Arbitrated Serial Ports have this.

J1  2x13 header with one missing through hole. Earlier versions had a double pin-row connector at that place ... intended for the (or: one) predecessor of the Systems Management Adapter used on "high availability network servers".

Diagnostic LEDs
   The 50-MHz Type 3 complex in a 90/95 (submodel code 28 and 29), has two LEDs; CR1 and CR2. During POST, CR1 comes on momentarily and CR2 stays off. If the LEDs work any other way, suspect that the processor board is defective. 

   Use the LEDs to help differentiate between a processor board or a system board failure. If you are instructed to replace one of the boards, and the problem still exists, replace the other board (also reinstall the first board). (Ed. Reports coming in make me wonder about any of this. If the board passes diagnostics, and works normally, do you really care about the LEDs?)

Enhanced Dual Path Memory Parts
The Type 3 has the 96F1920 Memory Data Buffer / 96F1921 Memory Address Buffer base board, 96F1992 Data Buffer / 78F1639 Address Buffer daughter card. The reason for the different chip numbers may be the use of "Packet Data Transfers" on the Adapter side I/O buffer.

* Enhanced dual path memory design (Dual Bus Interleave). Although Base 1 allows both the processor and busmasters to access memory concurrently through two paths, the Base 3 and 4 has buffers at both paths to provide better performance. Also the buffer on the adapter side (I/O buffer) uses packet data transfers for writes. This means 16 bytes are collected and this packet is written in one cycle to memory as opposed to writing for every 4 bytes received (as with unbuffered systems).

Daughtercard 71G6190

OS1 50 MHz CPU Clock SP1 71G6205 U1 87X0079 U2 78F1639 Memory Address Buffer U3 486DX-50 (5v)

U4,5,7-12 L2 Cache U6 96F1992 Memory Data Buffer U13,18 L2 Cache controller Set U14,15,17 TI SN74BCT 2160-12FM 0

U13, U18 L2 Cache Controller
U4, U5, U7-U12 Toshiba TC55B329J-12

Why DX50 is on Daughtercard
Peter spake thusly:
   The DX50 is on the daughtercard because of the odd Intel cache chipset. The chipset has limits on the distance it can be installed away from the CPU. The only was to use the CPU and cache together was to place them on a daughtercard.

Ed. Also think of the addition of the memory address buffers, which are as big as the Memory Data Buffers. You have to shoehorn in TWO fairly big chips, along with the discrete L2 cache, PLUS the L2 cache controller set.

Versions Incompatible with Network Streamers
   The downlevel processor card [FRU 57F1597] is identified by the lack of a module in position SP1. This card may cause data loss or undetected change in the:
   Lanstreamer MC 16 PN 58G8999
   Lanstreamer MC 32 PN 92F8941
   Etherstreamer MC 32 PN 59G9081

The upgraded FRU with SP1 is [FRU 82G2484] should be used with these cards.

Memory
Supports 1MB and 2MB 85ns memory, 2MB, 4MB and 8MB 70ns / 80 ns memory and 4MB and 8MB ECC 70ns memory.  The memory SIMMs must be installed in matched pairs (speed, size and type).
   All 64MB of memory are addressable by 32 bit DMA. SIMMs must be installed in pairs of matched speed and size. Mixing Parity and ECC is not allowed, not even if the pairs are matched.

  I have seen one card with the older BIOS 41G9251 ('92) that has NO rework. The three DX50 I have with the new BIOS 52G9619 ('93) all have the rework. Why? Haven't a clue.

Daughtercard Rework on Right

Daughtercard Rework on Left

False ARTIC diag error
   SYMPTOM: When running diagnostics on the ARTIC Portmaster Adapter/A in an 8590 or 8595 with the 486/50MHZ processor card installed, a false 14220, E0DE error may occur.
   PROBLEM ISOLATION AIDS: Check the date of the Portmaster Adapter/A diagnostic file (DEV141.DGS) on the system reference diskette. Files dated 1-31-90 or earlier will exhibit the symptom.
   FIX: Download updated Portmaster Adapter/A option diskette   Dead.

   So, the good news is that you could use almost any 2Mb PLCC32 EPROM or PROM that you can find to act as a replacement for the M5M27C201JK as the BIOS chip in your M complexi (where it is only being read by the system).  For programming the EPROM/PROM, you have to choose a part for which you have appropriate algorithms in your programmer, because they vary.

Jim Shorney
    Pay no attention to the manual.  Set the multiplier to x3, the cache jumper (if present) to write-through, and plug it in.  It will probably work fine.