On the 20-MHz board, jumper 2 must be on 1 and 2 if a 487SX processor is installed in position U1 . If there isn't a 487SX in U1 , the jumper must be on 2 and 3.

NOTE: When installing a CPU, align beveled corner with the beveled outline on the board.

NOTE: The "G" is the only Type 1 complex to lack a 160 pin L2 Cache option connector.

256 KB Cache Memory Option Kit,  17nS and 15nS [Work in Progress!]

NOTE: In a advertising/ tech nugget booklet, IBM ran tests with a number of [then] current applications, and the best they could do was 6%; that is, six percent. I bet they wanted much better.

17nS for "J" [25], "K" [33] and Upgrade 486DX2-66 [33] complexi
15nS for Upgrade 486DX-50 [50] MHz complex.

The 256 KB cache is a 5.5 x 3.0 inch card that connects to either the 25, 33 or 50 MHz complex. The connector is 160 pins arranged in four columns and 40 rows. The complex provides all the power required to drive the 256 KB cache.

256 KB cache memory option three basic logic elements:
   • 256 KB of SRAM
   • 4 KB of TAG SRAM
   • A cache controller.

  256 KB of Static Random Access Memory ["Data SRAM"]. This is two-way set associative, which allows each index location in the cache to store two pieces of information. This improves the hit ratio, and decreases the number of times that cache items must be removed to make room for new items.

  4 KB of "TAG SRAM" stores some of the cache item's address bits, used to store and locate the item, and some bits used for validity checking.

  "Cache Controller" coordinates access to the SRAM. On a cache-hit, the controller organizes the access of the data from the data SRAM using the TAG SRAM address. On a cache-miss, the controller places the new data into the cache, updating the TAG SRAM and data SRAM at the correct index location.

  The controller is also responsible for ensuring that the address being searched for is actually a cacheable address. If not, no cache search will be done.

256K Cache Not Visible under System programs?

64F0199, Back Side  

J1 159 Pin Header  AMP 650754-1 TD1  Fil-Mag 77Z14A030 TD2, TD4 Fil-Mag 77Z14A025 TD5, TD6 Fil-Mag 77Z14A045

U18-U21 IDT 74FCT646ASO U22, U23 TI T031XS AS573A U24-U27 Toshiba TC55329J-17 0

64F0199, Front Side   

U1-U4  Toshiba TC55329J-17 U5,6,8 TI SN74ACT2160-17FM U10 AMD 64F6043 U11 AMD 84F8257 U12 AMD 64F6065

U13 AMD 84F8261 U14 AMD 64F6046 U15 AMD 64F6048 U16 AMD 84F7970 U17 AMD 64F6066

Ed. The chips change from module to module. Yours may be different. I see no specific memory or cache controller chips [yet], the AMD chips are GAL/PALs, and they probably aren't the highest performance option...

92F0050 / 10G3527 Front Side  Thx to Lorenzo Mollicone

Huh, U11 is 10G3532. P/N is 10G3527. All the other PLCCs are 91F97nn.

92F0050 / 10G3527 Back Side  Thx to Lorenzo Mollicone 

Significant change from -17nS version. The 64F0199 uses five Fil-Mag Delay Modules and the -15nS uses ONE bel S423-0025-02 .

bel S423-0025-02 5 Tap Leading Edge Control Standard Delay Module HERE 

Motorola MC88915FN55 Low Skew CMOS PLL Clock Driver 55MHZ 28-PLCC 

How Does System Know That Cache Installed if it Doesn't show Up? 

On -17, U11 is 84F8257, different from most of the PLCCs. If I could see a sticker on the 64F0199, I bet it would be 84F82nn...

Patent: US5530887A Methods and apparatus for providing automatic hardware device identification in computer systems that include multi-card adapters and/or multi-card planar complexes

Example Multi-Card Adapter is the Image Adapter/A 
@8DF0.ADF - IBM Image Adapter/A
@8DF1.ADF - IBM Image/A and Printer/Scanner Option
@8DF2.ADF - DSS and sub card 2
@8DF3.ADF - DSS and sub card 3
@8DF4.ADF - IBM Image Adapter/A 3MB
@8DF5.ADF - IBM Image/A with Printer/Scanner Option

WBST and Major Tom, my SWAG is U11 stores a POSID for the L2 Cache option, and upon power on, the POSID for the complex is combined with that of the L2 cache, and that way, the system knows what is attached. It makes sense.

L2 Cache Performance
From Us, the god-Emperor of Microchannel
   Praytell, what use can one make of the 256K cache for the T1 complexes? I hate to admit it, but I never noticed a large (or significant) boost when I added one. 

From Tony Ingenoso
   The effects of modern bloatware on a write-through can be disheartening... IMO IBM's matched cycle scheme goes a long way towards helping keep the L1 lines filled at a brisk pace even when no L2 is present.  The T2's abnormally good performance (considering its other genetic limitations) shows this well.  For all practical purposes, 90/95's have a 64 bit memory subsystem working to fill the L1 lines.

From Charles Lasitter
   What do you see with one speed processors (DX50) that are coupled with a faster cache 64F0050, or the T3 and integrated cache? Since they don't have a 'fall back' processing speed in the event of an L1 miss, but rather use a 15ns L2 vs 17ns, is there any difference for them?
   I believe we've seen LARGE increases in speed when doing something like kernel rebuilds compared to no cache.  I think it may depend on what you're doing and the operating system.

From Tony

   I don't see this as a core multiplier issue -- even the low end DX25 T2 runs better than one might expect it to. The kernel rebuild improvements aren't surprising - compilation algorithms and the bits of data they work tend to be well localized if modules aren't too massive.  Initial parsing would be very read intensive as well and should make good use of an L2. Cache performance is indeed a very task specific kind of thing.  Scattered code/data can effectively neutralize it totally.

   DX50's are strange -- they often outrun DX2-66 when main memory bandwidth or I/O is the constraint.  When staying in L1, then the DX2-66 wins due to the multiplier.   With a fast L2 and fairly scattered code/data a DX50 is going to do very well.

From Peter
   Uhmmm ... I had the occasion to test a T1 DX2-33/66 board under Linux. And compare it with the same T1 DX-50 (!) board - both with the L2 cache. 

   The 486DX2-33/66 showed 33 BogoMips, the DX50 25 only ... same as the T3 DX50 while a DX2-50/100 (Intel DX4-100 in 2x mode) on a T3-platform runs at -supposed- 50 Bogomips almost.

   In the practical use the T1 DX50 wasn't much slower than the T1 DX2 - the XF86 stuff paced at the same rate on both. None of the machines "felt" faster or slower. The DX4 T3 was a bit faster - but not significantly. All 3 machines had the same XGA-2 card, the same TR 16/4 network adapter, the same 32MB Parity RAM and the same IBM 400MB HD with the Linux on it.

   The T1 platforms had the "plug on" 256K L2 cache (17ns on DX2, 15ns on DX50) and the T3 had its own integrated cache. I did not write down all the values ... maybe I should repeat that session again to get some definite, comparable data.

Complex BIOS Upgrade Needed for >1GB IML Drive 
   Type 1 complexes require the combination of BIOS 52G9509 and SCSI BIOS 92F2244/45 in order to handle IML drives >1GB (new limit is 3.94GB). The upgrade BIOS incorporates the 'Enhanced IML' which supports IML from a drive >1GB and "search IML" which allows IML from a drive other than ID6. The SCSI BIOS 44/45 pair supports drives well over 8GB. [Ed. You OS may have other ideas...]

From Tim Clarke
   After an extended E-mail exchange with Al Brandt, who couldn't get a machine to IML from a >1GB drive (SCSI ID. 6) attached to a SCSI-1 controller w/cache but with the notorious (now infamous?) 92F2244 and 92F2245 'Enhanced SCSI BIOS' ROMs using a Type-1 complex with either of the 'older' complex BIOS ROMs (i.e. 84F9154 for SOD Type-1 and 91F9812 for non-SOD Type-1), I decided to run my own tests.

   'Enhanced IML' in the complex upgrades is the *only* way to be able to IML from a drive >1GB (and from a drive Id. ¬= 6).

   At this time I must assume that the 92F2244+5 ROMs provide support for drives <= 4GB, but the 'old' complex ROMs' IML support somehow does not make (proper) use of it, possibly due to bad bit-shifting and/or masking when 'translating' the 'cylinder, head, sector' information to and from the SCSI 'logical block/sector' value.

From another thread
    BTW, space is usually allocated as a whole no. of cylinders, so the 'old' 3MB "System/Reference Partition" will grow to ~12MB on a >1GB drive.Albeit that only the 1st 3MB of that space is used/needed.

Some Other Thoughts 
From Charles Lasitter
   I've had some VERY entertaining results in my installations, depending on what other drives were present, and which version of the processor BIOS was used.

   With the 52G9509 in place, ID6 in bottom bay (Mod 95) at end of cable, ID5 in bay above on next spot on cable, I couldn't get the IML to go to ID6 to save my ass.  It made a beeline for ID5 every time.  Put in the old BIOS, and it goes straight for ID6.

Enhanced BIOS Effects
From Charles Lasitter
   As a result of a programming project with Mr. Clarke, I am now fairly certain that the odd behavior of an IBM SCSI controller "ignoring" ID6 to lay an IML track on a drive that was ID5 was really a function of the enhanced BIOS, which sniffs out the signature of any current or previous IML partition on a series of drives, and insists upon installing or recovering a system partition to that same location.

   This same feature is related to the IBM controller's inability to do an actual format of the drive if there has been an IML partition on the drive before.  The space at the end of the drive is never released, because the IBM controller refuses for format that area of the drive.

   That's why I typically use the RAID adapter when I REALLY want to nuke some drives. 

Upgrade EPROM Additional Capabilities  
    Type 1 complexes (except DX2-66 Upgrade, 92F0145) need BIOS 52G9509 to handle IML drives of >1,023MB. (U36 in drawing)
  1. More efficient use of Adapter ROM memory minimizes adapter configuration conflicts.
  2. BIOS support for IML drives up to 3.94 gigabytes per device.
  3. Supports "Search IML" from any PUN or SCSI ID.  System partition is no longer restricted to SCSI ID=6.  Each HD ID is searched for valid system partition.
  4. Allows redundant system partitions (IML).
  5. Sharing of SCSI devices.  An external SCSI device, (ex. 3511),  may be shared between two system units.

Complex EPROM Speeds  
   The normal EPROM speed is -120nS (or so). Other than the fact that the second stage of POST is contained on a mechanical device, how fast is stage 1 completed?

Peter replies:
   Original chips got 120 or 150ns where the total read cycle time does not even reach that. Depending on the wait states during BIOS access I would dare the guess that it is closer to 250ns for each word read. And while the ROM read speed is dependent on the total processor board cycle times it cannot be sped up somehow.

It is like using ZR-spec tires on an old '67 Mustang that would not even come close to the 300 km/h allowed for these tires ...

As you noted: the next part of the boot up runs off the HD but also at very carefully selected transfer speeds to allow even the slowest HD to cope with it. I don't think that using a faster HD (or FDD as well) would speed up the process significantly. The boot process has been designed to be carried out under worst case conditions to allow debugging or running a diagnostic tool afterwards (like CTRL-A). All of that includes a lot wait loops. If I were a better programmer I would flea out the BIOS for these and run it under the assumption that the HD could keep pace and get in the data as fast as possible ... and if *that* fails retry in a slower mode.  As far as I know they don't even use DMA to access the media but PIO.

Type 1 Complexi Upgrade to "8590/95 Dual Booting Capability EPROM"
  Complexi with the following EPROM part numbers may be upgraded:

PROCESSOR  FRU P/N   MODEL     EPROM P/N            LOC.
20MHZ SX   92F0049   0GX        91F9812             U36
25MHZ DX   64F0201   0JX       84F9154 OR 91F9812   U36
33MHZ DX   64F0198   0KX       84F9154 OR 91F9812   U36
50MHZ DX   92F0048   P3 (UPGD) 91F9812              U44
  It was called the "8590/95 Dual Booting Capability EPROM Package" 

PART NUMBER 52G9509 (was 52G9750 - try this if other PN is not known)

  NOTE:  Use the latest refdisk and diags. See above...

Weitek Abacus FPU by Axel Muhr

WeitekDisk.zip  Test suite from Weitek

"K" 486DX 33 MHz 64F0198   

190-186 IBM PERSONAL SYSTEM/2 486/33 PROCESSOR UPGRADE OPTION

The K complex has been seen in three guises:
   142 pin socket for Weitek 4167
   Solder pads, but no socket (SOD)
   No solder pads 

"Special K" (American breakfast cereal)
BIOS 84F9155 "IBM Confidential"
PCB is marked 64F5785 01 (right above U7)
54F2958 Memory Data Buffer (old)

Not So Special K
BIOS 84F9154 (unknown if 4167 flavored)
PCB is marked 64F5785 01
78F1659 Memory Data Buffer

It appears they share the same PCB, one has "IBM Confidential" / 54F2958, the other 84F9154 / 78F1659 (84F9154 likely a straight 486 BIOS)

Non-SOD Ks (Nothing where U8 was, just green resist)
FRU 64F0198
PCB is 92F1186 01
BIOS is 91F9812 (NOT Dual Booting Capability EPROM)
Uses the 78F1659 Memory Data Buffer

What is the SOD?
> What exactly is this square of death? (SOD)?
It is the mark of the beast. This square of solder pads is actually the binary equivalent of 666.

David Beem responds:
     The missing A1 & A2 pins make this a dead giveaway for the Weitek 4167. Steven Wachtel reports "memory management" problems (ECA #0530) with the SOD complex, which might make sense since the Weitek processors use high memory areas to transfer op codes. So, can a socket go in place to see if a 4167 would be functional there, or was it a dropped option? I suppose that with a couple SOD T1s (one of each of the patches talked about in this thread) & a Weitek 4167 I am one of those that could answer the question.

>Regarding the sensitivity of this complex, has anyone ever tried to swap the BIOS with another Type 1 complex that is known to work with the faster CPUs?

     Despite the complexi being very similar & using the same reference disk, fundamental changes for things like the Weitek coprocessor could really mess things up. IBM would issue a whole complex if there was problems, not just a BIOS change. Other than the T4 'N' I have seen no evidence of other complex types checking things like CPUID.

Peter adds:
   The only reflection from the past is the comment of an IBM employee confronted with that exact question. He said "Forget about it". He then added that the complex had been designed at a time when IBM was yet "Big Blue" and tended not to give too much control over their products to one OEM and they therefore integrated provisions for a "non-Intel" MCU (the Weitek), but the full integration never came.

   Practically the SOD can be judged as an analog to the "spare" dual-in-line artifact solder spots that can be found on many cards, where the developers planned to build "something" but weren't sure what it could be and how it should look. Reserve spots in a way suitable for add-ons or patches, barely attached to the whole board - apart from power, GND and some basic address / data / signal lines. The outline matches the Weitek math-co, but it is (after my knowledge) not supported from neither the glue logic nor the platform BIOS.

SOD Limitations from Tim Clarke
   The limitation of the 'poor DMA controller' for the Type-1 SOD board appears to be that you can't run a Cyrix/IBM 5x86 at greater that 'x2 clocking' (i.e. 50Mhz in a Type-2, 66Mhz in a Type-1) or an AMD 586 at greater than 'x3 clocking' (i.e. 75Mhz in a Type-2, 100Mhz in a Type-1). Ed. You CAN run a 486DX4-100 ODPR on a SOD. It's only a 3x multiplier.

   Not having a SOD Type-2 I can't test this, but I would expect the same limits to apply. So, you should be able to run a DX2-50, DX2-ODPR (@ 50Mhz), Cyrix/IBM 5x86 (@50Mhz) or AMD 586 (@ 75Mhz) in a SOD Type-2. The 'performance' of a Cyrix/IBM 5x86 @ 'x2 clocking' and the AMD 586 @ 'x3 clocking' are *roughly* equal, although I have a preference for the Cyrix/IBM chip.

ECA #0530 90-0K9/95-0KD with Complex P/N 84F9356

Steven Wachtel wrote:

   These systems appear to have a memory management problem. In my environment it was seen on a Model 90 with 16 MB of RAM. The system would hang during OS2 boot or during invocation of simple processes after a basic install (such as the system editor ). Symptoms at other OS2 sites would include excessive "random" trap errors. Not using DOS on these systems, I would expect the problem to surface as some indeterminate memory related failure in the E/XMS region.

    During initial setup of this machine, the problem appeared as an inability to create a usable backup reference disk ( if said disk was used there were always errors ).  On restart after the failure the machine will request to exec its own auto-reconfiguration and mark out the "bad" regions.  For my situation I had the IBM CE on-site for ~6 days for two separate events.  The CE changed each memory chip and riser (for the M90) multiple times and recombined them in every combination representation. 

   Today (11/5/91) after following his instincts and direction of the higher level support reps, he contacted them again. They asked for the part number of the CPU board, upon which rests a Gate Array based custom memory controller.  He was advised that there are *known* problems with the down-rev boards in my new machines. This problem exists(ed?) on the 0KD models of the M90 and M95, and possibly (as I do not have any to verify this ) the 0JD models.  IBM's second level support is apparently aware of this potential problem, but has not disseminated this to the CE level or the purchasing customer. 

Problem part identification and rectification:
   If the Processor Complex ( nee-CPU board ) part number is 84F9356 ( or 84F anything ? ) on the "barcode/label" of the board you should get a replacement. 
   The replacement part bears the part number 92F.....  I do not know if this is free.  Note, I have a M95 with this later board version that has never shown any of these problems.

192-178 IBM PS/2 486DX2-66 PROCESSOR UPGRADE OPTION

J4- Once you toggle this jumper you will end up in a 0129 3000 error - "EEprom Jumper is in the wrong position" and no boot or such. I'd reported that some time ago while testing around with the 92F0145.

  Most likely it was originally intended to give the -0145 with 2 banks of EEprom to choose between - but by what reason they installed only one bank and the alternative setting branches into a BIOS error-code instead.

NOTE: Leave J4 jumper on the center and bottom pin, "R"

Peter sez:
   As a follow up notice: Yes - it *has* a flash-BIOS. And - Yes - it comes up with the Type-1 reference disk. Even installs a reference partition as usual with these disks.

   But the system permanently fails to boot into this Type 1 reference partition. Once you reboot it and press [ctrl]+[alt]+[ins] at CP 66 (cursor top / right) the machine loads the operating system instead jumping into reference.

   The platform nicely takes the Kingston Turbochip *without* restoration of the system partition. Runs fine with it - right from the start.

Supports Non-IML Configurations
  Dennis Smith found out that this complex can successfully boot without an IML device at ID6. He booted a SCSI drive at ID0 WITH NO IML track. I did it here with my upgrade DX2-66.

   His guess was this complex was designed to support RAID Arrays, and the early RAID controller, "Passplay" had no ability to boot from an array.

191-096 Personal System/2 486/50 Processor Upgrade Option  [Type 1 486/50]
15nS L2 Cache- 92F0050  NOTE: This complex needs the 15nS cache.
52G9509 "8590/95 Dual Booting Capability EPROM" HERE 
        Uses the standard Type 1 EPROM, 27010 / 27C010
Complex BIOS Upgrade Needed for >1GB IML Drive   
SCSIFIX.ZIP Utility to alter # of SCSI drive sectors and convert to a 3.94GB drive!

Peter
   As far as I can tell (from the pictures of that complex) it varies through some different wiring and modified ASICs. The part of the hardware that deals with the CPU clock generation looks a bit different. The rest of the card is the "later" Non-SOD Type 1 platform as I have it here in my trusty old AKD.

U44 Complex BIOS Stock version is 91F9812. This version does not fully support the F/W SCSI [Corvette] and IML from up to 3.94GB drives.

To get the most out of this complex, you need the 52G9509 "8590/95 Dual Booting Capability EPROM" -AND- the SCSI adapter needs the 92F2244 and 92F2245 SCSI BIOS Firmware. All three can Spocks, short Tribbles, and all Fast/Wide SCSI adapters come stock with the 44/45 SCSI BIOS pair.

Some observations-
The chipset appears the same as other Type 1s with the addition of decoding circuitry.

The Upgrade 486DX-50 is a Type 1 with true 50MHz CPU on the complex! All Type 1 complexi [except "G"] use a 160 position 4x40 receptacle for the L2 Cache option. Having the 486DX-50 on the complex PCB instead of a daughtercard means that any upgrade CPU will NOT be getting close to a Model 90 memory riser!

NOTE: On the Upgrade 486DX-50, the CPU clock, OSC1, has been moved from being under the left side of U16. It is visible even with an L2 Cache option installed. OSC1 is a black SMD, so if you don't see a shiny oscillator like you are used to, look again.

NOTE: The Type 3 "M" complex is the only other true 486DX-50, but the "M"'s DX-50 is on the daughtercard! [M is also called the "double-decker"]

NOTE: The Type 3 "M" complex is the "Enhanced 486/50" while the Type 1 486/50 is the "486/50 Processor Upgrade"

To positively identify the Upgrade 486/50, look at the back for the FCC ID sticker. I have noticed that sometimes, an older complex that was replaced is put into the box from the upgrade.